The present invention relates to a memory fault analysis apparatus for analyzing whether an analyzed memory having a redundancy circuit is faulty or not, and whether replacement with a redundancy circuit is possible.
In general, a memory fault analysis apparatus performs individual fault analysis for the memory cells of a memory that has redundancy circuits and which is being analyzed, and when there is a faulty memory cell, it is judged that a redundancy circuit can save the fault. FIG. 1 shows a conventional memory fault analysis apparatus. This memory fault analysis apparatus is provided with an algorithmic pattern generator (hereinafter termed an ALPG) 2, a comparator 4, and a fault analysis memory (hereinafter termed a FAM) 8. First, address signals and data signals for testing are sent from the ALPG 2 to a memory under test (MUT) 50 which is a memory having a redundancy circuit, and read is performed after data has been written to memory cells of the MUT 50 and in accordance with these address signals. Then, the written data and the read data are compared by the comparator 4 and fault signals are sent to the FAM 8 if the two are different. This FAM 8 has a memory area that is the same size as the memory cell array of the MUT 50, and each of the memory cells of the FAM 8 are allocated the same address as a memory cell that corresponds to the MUT 50. Then, when a fault signals is used from the comparator 4, the data "1" is written to the corresponding memory element of the FAM 8 . More specifically, as shown in FIG. 2A for example, when there is a fault in a memory cell having the row address X.sub.4 and the column address Y.sub.0 of the MUT 50, then as shown in FIG. 2B, the data "1" is written in the row address is X.sub.4 and the column address is Y.sub.0 of the corresponding memory cell. In the following, the address of a memory cell having the row address X and the column address Y is simply expressed as (X, Y). In the same manner, when there is a fault in memory cells that have the addresses (X.sub.1,Y.sub.1) and (X.sub.3,Y.sub.3) in the MUT 50, data "1" is written in the memory cells of the FAM 8 that have the addresses (X.sub.1,Y.sub.1) and (X.sub.3,Y.sub.3). Moreover, the memory cells of the FAM 8 are initialized so as to store the data "0" prior to the performance of analysis processing.
In this manner, the address signals and the data signals from the ALPG 2 are used as the basis for analyzing whether or not each of the memory cells in the MUT 50 has a fault, and for writing "1" to corresponding memory cells in the FAM 8 when there is a fault. The data which is written to this FAM 8 is used as the basis for a judgment apparatus not shown in the figure, to judge whether or not the MUT 50 can be saved by a redundancy circuit.
In a conventional memory fault analysis apparatus such as described above, it is necessary to have a FAM 8 that has a large-capacity measurement memory of the same size as the MUT 50 and so it is necessary to have a FAM 8 having an extremely large memory for the analysis of large-scale memories and for simultaneous analysis of a plural number of memories. For example, if sixteen memories each having a storage capacity of 4 Mbits for example are to be analyzed, then it is necessary to have a FAM that has a minimum capacity of 64 Mbits. Then, when the capacity of the FAM 8 becomes larger, there is the problem of a large increase in the judgment time for whether or not recovery is possible by a redundancy circuit.